1. Field of the Invention
The present invention relates to an organic light emitting display device and a method for manufacturing the same, and more particularly, to an organic light emitting display device configured to prevent shorts from being generated in a capacitor region and a pixel region, and a method for manufacturing the organic light emitting display device.
2. Description of the Related Art
According to a proliferation of display devices along with the rapid advances in the information communication industry, display devices, meeting requirements of low power consumption, lightness in weight, slimness, a high resolution, and so on, have recently been required. To keep up the pace with such requirements, liquid crystal displays or organic light emitting displays using organic electroluminescence are being developed.
An organic light emitting display is a next-generation display device having a self-emissive characteristic, and is superior in view of viewing angle, contrast, response speed, and power consumption, compared to a liquid crystal display. In addition, the organic light emitting display does not require a back light, so that it can be produced as a lightweight, slim display.
The organic light emitting display includes a substrate that provides for a pixel region and a non-pixel region, and a container or a member disposed to face the substrate and adhering to the substrate by a sealant made of, for example, epoxy, for encapsulation. A plurality of light emitting devices forming pixels are formed between scan lines and data lines in the pixel region of the substrate in a matrix type. In the non-pixel region, scan lines and data lines extending from the scan and data lines of the pixel region, power voltage supply lines for operating the organic light emitting display, and a scan driver and a data driver for processing signals externally supplied through an input pad and supplying the processed signals to the scan lines and the data lines.
The organic light emitting display includes a pixel region, a transistor region and a capacitor region that maintains a driving voltage at a constant level. A conventional capacitor is formed by allowing a gate electrode and portions of source/drain electrodes for forming a thin film transistor to remain in the capacitor region.
Recently, an IOS capacitor is formed by allowing a semiconductor layer and a portion of a transparent electrode disposed on the semiconductor layer for forming a thin film transistor to remain in the capacitor region.
To form a capacitor using a transparent electrode, the transparent electrode and a gate electrode formed thereon are blanket etched. Here, the blanket etching of the transparent electrode and the gate electrode using a single etching stopper film allows the transparent electrode 5 formed under the gate electrode 6 to protrude outwardly relative to the gate electrode 6, as shown in FIG. 1a. 
Since the thus-formed transparent electrode 5 protrudes outwardly relative to the upper gate electrode 6, a portion of the when the transparent electrode 5 may be etched in a subsequent process in which the interlayer dielectric film 7 is formed and patterned using the same, thereby forming a byproduct of the transparent electrode 5. Since the byproduct of the transparent electrode 5 is a conductive material, unintended electrostatic discharge (ESD) or electric short may be generated. The transparent electrode 5 is formed not only in the capacitor region but in the pixel region. As described above, since the blanket etching of the transparent electrode 5 in the pixel region and the gate electrode 6 allows ends of the transparent electrode 5 to protrude outwardly relative to the gate electrode 6, the ESD or electric short may be generated, like in patterning the interlayer dielectric film 7.
Further, as shown in FIG. 1b, in a case where the portion of the lower gate insulation film 4 is also etched when the interlayer dielectric film 7 is formed on the capacitor region C, a terminal portion of the transparent electrode 5 disposed on the gate insulation film 4 may sag downwardly or may get closer or come into contact with the semiconductor layer 3 exposed by the etched gate insulation film 4, resulting in a high risk of short defect S.